Current charge-based semiconductor storage technologies such as SRAM, DRAM,
NOR flash and NAND flash face scaling challenges as geometries shrink below
20nm. As a result, a marked increase in research activity focused on
alternative memory technologies has occurred over the last decade.
Non-charge storage-based memories such as FeRAM and MRAM offer fast RAM-like
performance along with non-volatility and extremely high endurance. Although
in commercial production, both suffer from high costs vis-a-vis current
technologies and have only been able to address niche applications.
All that is likely to change with the availability of samples of in-plane
spin-torque transfer MRAM (STT-MRAM) from Avalanche Technology and Everspin
Technologies. These achievements are a stepping stone to next generation
perpendicular STT-MRAM which promises a scalable path with the potential to
broaden its appeal into mainstream consumer applications. As a consequence,
the embedded and standalone non-volatile RAM markets are on the cusp of
explosive growth in the next few years.
A Magnetic Moment: Prospects for MRAM Technology, Markets and Applications
offers an independent view of the opportunities and challenges presented by
MRAM technology and its potential as one of the leading contenders in the
emerging memory space.
Table of Contents
Table of Contents
Contents
List of Figures
List of Tables
Executive Summary
Memory Overview
Introduction
The Memory Hierarchy
SRAM
Concept
Technology Evolution
DRAM
Concept
Technology Evolution
NOR Flash
Concept
Technology Evolution
NAND Flash
Concept
Technology Evolution
Ferroelectric Memories
Ferroelectric Random Access Memory (FeRAM)
Ferroelectric Transistors (FeFET)
Phase Change Memory
Concept
Basic Operation
Other Resistive Switching Memories
MRAM
Introduction
Conventional Design
Toggle MRAM
Concept
Materials for the Toggle-MRAM:
Thermal Assisted Switching TAS-MRAM
Concept
Materials for the TAS-MRAM
Spin-Transfer Torque (STT) MRAM
Concept
Materials for the STT
Thermal Stability and Retention
Write Margin vs. Reliability
Scalability
Materials with Perpendicular Magnetic Anisotropy (PMA)
Domain wall (DW) motion MRAM
Concept
Materials for the DW-Motion MRAM Cell
Increasing the Bit Density With Multi Level Cells (MLC)
MLC Based on Single MTJs
MLC Based on Parallel Connected MTJs
MLC Based on Series Connected MTJs
MLC Based on Domain Wall Motion
MLC Programming
Two-Step Programming
Probabilistic Programming
Design and Architecture
STT-MRAM Cell Design
1T-1MTJ
2T-1MTJ
Shared Source-Line (-Plane)
Selection Device
Sensing Schemes
Data Retention Relaxation
Racetrack Memory
MTJ in non-volatile logic
Introduction
Non-volatile Latch/Flip-Flop
Non-volatile Adder
Non-volatile Look-up Table (LUT)
Spin-logic
MRAM Fabrication
Process flow
Element shape
3D Integration
MRAM Cost Drivers
Process Complexity
Cell Efficiency
Yield
Cost per Bit
Memory Comparison
MRAM Characteristics
Switching Time
Current / Power Consumption
Retention Time
Endurance and Wear Leveling
ECC
Scaling
MRAM vs. DRAM
MRAM vs. Flash
MRAM vs. SRAM
MRAM vs. FeRAM
MRAM vs. PCM
Roadmap
MRAM Status
Aeroflex, Inc.
Avalanche Technology
Crocus Technology
Everspin Technologies, Inc.
Freescale Semiconductor
Hitachi Ltd.
Honeywell International, Inc.
IBM Corp.
Infineon Technologies AG
Intel Corp.
Magsil Corporation
Micromem Technologies, Inc.
Micron Technology
NEC Corp.
NVE Corp.
Qualcomm, Inc.
Renesas Technology
Samsung Electronics
SK Hynix Semiconductor
Spin Transfer Technologies
Spingate Technology LLC
SPINTEC
ST Microelectronics
Taiwan Semiconductor Manufacturing Company
Toshiba Corp.
Tower Semiconductor Ltd.
Market and Applications
Introduction
Embedded MRAM Market
Requirement For Successful eMRAM Market Entry
Processor Companion Devices with Battery-backed SRAM and Real-time
Clock
Set-top box MCU using EEPROM or Battery-Backed SRAM
RF ID Devices, Smartcards, and e-Passports
Smart Meters
Mobile Baseband SOCs
Mobile Application Processor SoCs
Embedded nvRAM Market Forecast
BB-SRAM
FERAM
nvSRAM
MRAM
Market for nvRAM Product Revenue by Technology
Embedded MRAM Market and Applications Outlook
Standalone MRAM Market
Memory Market Segmentation Based Upon Price/Bit and Feature Sets
Differentiation
MRAM as an SRAM Replacement
MRAM as a Non-volatile RAM
RAID Write Index Application
SmartMeter Datalog Application
Other nvRAM Applications
MRAM as a DRAM Replacement
High Density DRAM-compatible MRAM Applications
Instant-on Embedded Controller Memory
RAID Non-volatile Cache Memory
HDD Non-volatile Buffer Memory
Enterprise SSD Metadata Cache/Buffer
Mobile Chipset Memory
MRAM as a Storage Class Memory
Standalone MRAM Market and Applications Summary
References
About the Authors
About Forward Insights
Services
Contact
About NamLab
Contact
List of Figures
Figure 1. Memory Hierarchy
Figure 2. SRAM Cell Schematic
Figure 3. Monolithic 3D SRAM Technology
Figure 4. DRAM Cell Schematic
Figure 5. DRAM Cell Transistor Evolution
Figure 6. DRAM Cell Capacitor Trend
Figure 7. NOR Flash Cell (ETOX: EPROM thin oxide cell)
Figure 8. NOR Architecture
Figure 9. NOR Flash Cell
Figure 10. NOR Flash Technology Evolution
Figure 11. Drain Bias Margin
Figure 12. Multi-bit Charge Trapping Cell
Figure 13. NAND Architecture
Figure 14. NAND Cell String
Figure 15. NAND Flash Technology Evolution
Figure 16. NAND Flash Memory Gap Fill at 63nm and Flat Memory Cell at
20nm
Figure 17. Electrons Stored on the Floating Gate
Figure 18. Operation of a FeRAM Memory
Figure 19. Ferroelectric Field Effect Transistor
Figure 20. Basic PCM Cell Structure and Cell Operation
Figure 21. Resistive Switching Effects
Figure 22. MRAM-Cell Requirements
Figure 23. Schematic View of (a) Field-Induced Switching MRAM and (b)
STT MRAM.
Figure 24. MRAM Operation with Field-Induced Switching
Figure 25. Switching Field Threshold for Permalloy Magnetic Elements of
Different Ends.
Figure 26. Program Operation in the Toggle Switching Scheme MRAM Design
Figure 27. Toggle-MRAM Cell with a Select Transistor
Figure 28. MTJ Layer Stack and the Uniformity Requirements
Figure 29. Writing Procedure for (a) a Conventional MRAM Cell and (b)
TAS MRAM Cell
Figure 30. MTJ Design for a) Conventional Field Driven Approach and b)
TAS Approach
Figure 31. Architecture of a TAS-MRAM Memory Array
Figure 32. Influence of the Thickness of an IrMn Layer on the Exchange
Bias Field
Figure 33. Area Dependency of the Write Power for a TAS-MRAM Cell
Figure 34. TAS-MRAM Cell Material Stack and Write Power Density vs.
Junction Area
Figure 35. Material Stack for a Double Barrier MTJ with one Thermal
Barrier
Figure 36. Spin Torque Transfer MRAM Concept
Figure 37. Schematic View of a Typical STT Memory Element and TEM
Cross-Section
Figure 38. Illustration of the Spin Polarization Enhancement for a Dual
Barrier Structure
Figure 39. Normalized Switching Current Thresholds vs.
Magneto-Resistance Ratio
Figure 40. STT-MRAM Write Current Scaling for Different MTJ Structures
Figure 41. Required Room Temperature Values for ΔH
Figure 42. Calculated Single Bit Cycle to Cycle Read Error Rate for
three ΔI Values
Figure 43. Measured Critical Switching Voltage and Break Down Voltage
Distributions
Figure 44. Switching Probability vs. Switching Pulse Width
Figure 45. BER Curves Showing a Bifurcated Switching,
Figure 46. Planar MTJ Scaling: Thickness and Switching Current Density
vs. Cell Width
Figure 47. Comparison of (a) In-Plane STT-MRAM and (b) Perpendicular
STT-MRAM.
Figure 48. Illustration of Perpendicular STT-MRAM Design
Figure 49. Scaling of Critical Switching Current for In-Plane and
Perpend. MTJ Elements
Figure 50. Possible Cell Structure and Operation Principle of the
DW-Motion MRAM Cell
Figure 51. DW-Motion Cell Structure a) and Cross-Sectional TEM Image b)
Figure 52. DW-Motion Velocity in a Co/Ni Nano-Laminate Free Layer
Figure 53. MLC in Single MTJs - Calculated TMR Ratio
Figure 54. Schematic Illustration of MLC-MTJ
Figure 55. MLC STT-MRAM Cell with Series Connected MTJs
Figure 56. Stacked MTJ Cell Fabrication and Bit Cost Scaling
Figure 57. MLC with Field Compensation Layer
Figure 58. Schematic Representation of MLC Cell Based on Domain Wall
Motion
Figure 59. State Transition Graphs of Write Schemes
Figure 60. Probabilistic Programming
Figure 61. 1T-1MTJ STT-MRAM Structure
Figure 62. 2T1MTJ Structure and Layout
Figure 63. Shared SourceLine: a) Schematic and b) Layout
Figure 64. MTJ Current Scaling Compared to the Current Scaling of
Select Devices
A Magnetic Moment: Prospects for MRAM Technology, Markets and Applications published by Forward Insights in January 1, 2013. This report consists of 155 Pages and the price starts from US $ 14999.
