Multicore Processors Drive the Software-Defined Network: A Heavy Reading Competitive Analysis

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Market Research Report Multicore Processors Drive the Software-Defined Network: A Heavy Reading Competitive Analysis
Published by	Heavy Reading
Published	September 30, 2012	Product code	251780
Content info	67 Pages
Price	USD 3995 PDF by E-mail (Single User License)

Introduction

Introduction

Abstract

Multicore processors are the key to meeting carriers' and other customers' demanding requirements for flexible systems and multicore processors are now the heart of almost every type of networking device. This allows network system developers to define much of the network functionality in software and make systems more flexible to support industry developments such as OpenFlow and software-defined net-working. Multicore processors are highly integrated system-on-chip devices with up to 100 cores and hardware acceleration for security and low-level packet processing. Multicore processors can be pro-grammed in C or other high-level languages and are directly supported by multicore operating systems and applications software from companies such as 6WIND, Enea, and Wind River.

The market for multicore processors in networking continues to grow. Many companies are using com-mon blades with multicore processors for a wide range of functions. This reduces development costs and allows telecom equipment manufacturers to use standardized platforms such as ATCA. Most multicore processor vendors now have a range of devices with different numbers of cores and hardware acceleration engines. This allows system developers to meet a range of different performance and functional demands using multicore processors that are software compatible across all their systems.

The first integrated multicore processors, using 130nm and 90nm technology, were introduced in 2004. The development of 40nm, 32nm and 28nm silicon technology has allowed the integration of significantly more memory, high-performance cores, and enhanced network interfaces. Most multicore processor ven-dors have announced new solutions in the last year. The latest multicore processors integrate up to 20MB of cache memory, up to 500 hardware accelerators, and significantly more than 100Gbit/s networking I/O bandwidth.

Multicore Processors Drive the Software-Defined Network: A Heavy Reading Competitive Analysis surveys vendors developing high-performance multicore processors. As such, it not only provides granular information on the components themselves - of interest to chip manufacturers and purchasers - but also provides insights into how the overall market for multicore processors is likely to develop - of interest to a wide audience, including carriers and investors.

This report is based on interviews conducted with 16 multicore processor, IP core and software vendors, and product documentation supplied by these vendors. Most interviews were conducted during the se-cond quarter of 2012. These in-depth interviews offer insight into how the market for multicore proces-sors is likely to develop in the future. For a full list of companies analyzed in this report, click here.

This report analyzes the multicore processor market by parsing devices into three groups:

General-purpose multicore processors: Multicore processors based on general-purpose CPUs that can be used in high-performance networking systems
Integrated multicore processors: Multicore processors with integrated packet processing instructions, hardware acceleration engines, and networking-specific interfaces
10/100-Gbit/s network processors: Network processors with a mix of high-performance packet engines and hardware acceleration engines

The report contains detailed information on more than 80 devices or groups of devices. The tables pre-sented in the report were compiled using data provided during these interviews and from product docu-mentation. Once the tables were compiled, the relevant data was provided to all the vendors for confirmation, feedback, and updating.

The excerpt below shows the latest multicore processor family developed by NetLogic, recently acquired by Broadcom. The 40nm XLP processor builds on the 90nm XLR architecture developed by RMI. The NetLogic multicore architecture is built around a shared memory switch that connects the eight MIPS64 cores and distributed interconnects to the 8MB Layer 3 cache, memory controllers and networking I/O.

Report Scope & Structure

Multicore Processors for Network Systems: A Heavy Reading Competitive Analysis is structured as follows:

Section I includes a full executive summary and report key findings.

Section II presents an overview of multicore processor applications and architectures, including generic block diagrams.

Section III focuses on general-purpose multicore processors, including detailed vendor profiles and a competitive analysis of products now in production and announced products not yet available in produc-tion quantities. Full details for these products are presented in Appendix A.

Section IV covers integrated multicore processors, with detailed vendor profiles and full feature comparisons for current and forthcoming offerings. Full details for these products are presented in Appendix B.

Section V includes detailed vendor profiles and full feature comparisons for both current and announced 10- to 100Gbit/s network processors. Full details for these products are presented in Appendix C.

Multicore Processors for Network Systems: A Heavy Reading Competitive Analysis is published in PDF format.

LIST OF FIGURES3

I. INTRODUCTION & KEY FINDINGS

1.1 Key Findings
1.2 Report Scope & Structure

II. MULTICORE PROCESSOR APPLICATIONS & ARCHITECTURES

2.1 General-Purpose Multicore Processor Architectures
2.2 Integrated Multicore Processor Architectures
2.3 Network Processor Architecture
2.4 Multicore IP
2.5 Multicore Software

III. GENERAL-PURPOSE MULTICORE PROCESSORS

3.1 Advanced Micro Devices
3.2 Intel

IV. INTEGRATED MULTICORE PROCESSORS

4.1 Integrated Multicore Processors in Productio
4.2 Latest Integrated Multicore Processors
4.4 Applied Micro Circuits Corp
4.4 Broadcom Corp
4.4 Cavium Networks
4.5 Freescale Semiconductor
4.6 LSI Technologies.35
4.7 Marvell Technology Group Ltd
4.8 Tilera Corp

V. 10- TO 100-GBIT/S NETWORK PROCESSORS

5.1 Leading Network Processors in Production
5.2 Latest Network Processors
5.3 Broadcom Corp.
5.3 EZchip Semiconductor
5.4 Marvell (Xelerated)
5.5 Netronome Systems

APPENDIX A: CONTROL PROCESSORS

APPENDIX B: INTEGRATED MULTICORE PROCESSORS

APPENDIX C: 10- TO 100-GBIT/S NETWORK PROCESSORS

APPENDIX D: ABOUT THE AUTHOR

APPENDIX E: LEGAL DISCLAIMER

LIST OF FIGURES

SECTION I

SECTION II

Figure 2.1: Typical Multicore Processor-Based ATCA Blade
Figure 2.2: General-Purpose Multicore System
Figure 2.3: Typical General Purpose Chipset Integration
Figure 2.4: Typical First-Generation Multicore Processor
Figure 2.5: Typical Third-Generation Multicore Processor
Figure 2.6: Typical VLIW-Based Network Processor

SECTION III

Figure 3.2: AMD Opteron 6100 Series Block Diagram
Figure 3.3: AMD Opteron Multicore Processors
Figure 3.4: Intel 5100 System Diagram
Figure 3.5: Intel Xeon Multicore Key Parameters
Figure 3.6: Intel Xeon C5500 System Diagram
Figure 3.7: Intel Xeon Multicore Processors
Figure 3.8: Intel Xeon E2400/2600 System Diagram

SECTION IV

Figure 4.1: Leading Integrated Multicore Processors in Production
Figure 4.2: Leading Integrated Multicore Processor Architecture
Figure 4.3: Leading Integrated Multicore Processor Interconnects
Figure 4.4: Latest Integrated Multicore Processors
Figure 4.5: Latest Integrated Multicore Processor Architecture
Figure 4.6: Latest Integrated Multicore Processors Interconnects
Figure 4.7: Applied Micro X-Gene Platform
Figure 4.8: Applied Micro Multicore Processor Key Parameters
Figure 4.9: Broadcom BCM1480 Multicore Processor
Figure 4.10: Broadcom Multicore Processor Key Parameters
Figure 4.11: Broadcom Multicore Processors
Figure 4.12: Broadcom XLP Multicore Processor
Figure 4.13: Cavium Multicore Key Parameters
Figure 4.14: Cavium CN68xx Octeon II Processor Family
Figure 4.15: Cavium CN7xxx Octeon III Processor Family
Figure 4.16: Cavium Multicore Processors Summary
Figure 4.17: Cavium Multicore Processors Interfaces
Figure 4.18: Freescale QorIQ Multicore Platform
Figure 4.19: Freescale QorIQ Multicore Key Parameters
Figure 4.20: Freescale QorIQ AMP Series T4240 Processor
Figure 4.21: Freescale QorIQ LS-2 Processor
Figure 4.22: Freescale Multicore Processors Summary
Figure 4.23: Freescale Multicore Processors Interfaces
Figure 4.24: LSI ACP3400 Axxia Multicore Processor
Figure 4.25: LSI Axxia Key Parameters
Figure 4.26: LSI Multicore Processors
Figure 4.27: Marvell Armada XP Multicore Processor Key Parameters
Figure 4.28: Marvell Multicore Processors
Figure 4.29: Tilera TILE64 Multicore Processor
Figure 4.30: Tilera Multicore Key Parameters
Figure 4.31: Tilera Multicore Processors

SECTION V

Figure 5.1: Leading Network Processors in Production
Figure 5.2: Leading Network Processor Interfaces
Figure 5.3: Leading Network Processor Memory & Traffic Manager
Figure 5.4: Latest Network Processors
Figure 5.5: Latest Network Processor Interfaces
Figure 5.6: Latest Network Processor Memory & Traffic Manager
Figure 5.7: Broadcom Network Processors
Figure 5.8: EZchip NP-4
Figure 5.9: EZchip Network Processor Key Parameters
Figure 5.10: EZchip Network Processors Overview
Figure 5.11: EZchip Network Processor Interfaces
Figure 5.12: Xelerated Network Processor Key Parameters
Figure 5.13: Xelerated HX Family
Figure 5.14: Xelerated Network Processors Overview
Figure 5.15: Xelerated Network Processor Interfaces
Figure 5.16: Netronome NFP32xx
Figure 5.17: Netronome NFP & Intel 28xx Key Parameters
Figure 5.18: Netronome NFP-6xxx
Figure 5.19: Netronome Network Processor Interfaces

APPENDIX A

Figure A.1: General-Purpose Multicore Processor Summary
Figure A.2: General-Purpose Multicore Processor I/O

APPENDIX B

Figure B.1: Integrated Multicore Processor Summary
Figure B.2: Integrated Multicore Processor I/O

APPENDIX C

Figure C.1: 10- to 100-Gbit/s Network Processor Summary
Figure C.2: 10- to 100-Gbit/s Network Processor Architecture
Figure C.3: 10- to 100-Gbit/s Network Processor I/O

Multicore Processors Drive the Software-Defined Network: A Heavy Reading Competitive Analysis published by Heavy Reading in September 30, 2012. This report consists of 67 Pages and the price starts from US $ 3995.