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The Global Market for Equipment and Materials for IC Manufacturing

Abstract

Up to 11 layers of wiring with a cumulative wire length >1.4km will be used on a 10mm square microprocessor introduced in 2007. In a typical MPU cross-section, tungsten studs in a planarized PSG pre-metal dielectric layer are typically used to make contact between the copper Metal 1 layer and the device gate and diffusions. A single damascene process is used for Metal 1, and the product layout uses staggered contacts to allow for the tightest pitch. A dual-damascene process is used for subsequent intermediate and global wiring layers. All Cu wires are encased by a metallic diffusion barrier on sidewall and bottom regions, and by a dielectric capping layer on top of the wire that also functions as a diffusion barrier.

CMOS-based devices will remain “the industry workhorse” beyond 2020, although it also states that new devices appearing toward the end of the next decade will use new methods of processing and storing information. Because most of these products will require new materials, a subchapter was added in a new separate section covering emerging devices.

This report examines and projects the technologies involved in the fabrication of VLSI semiconductor devices, their likely developments, why and when their introduction or demise will take place, what problems and choices are facing users, and where the opportunities and pitfalls are. It is written from an industry perspective.

The 350 processing steps required to make an integrated circuit (IC) entail the use of chemicals and equipment, all housed in a contamination-free environment or cleanroom.

This report discusses the technology trends, products, applications, and suppliers of chemicals (liquids and gases) and equipment (lithography, mask making, plasma etching, deposition, CMP, automation, and metrology).

This report is written for the purpose of assisting the reader in evaluating the spectrum of products, packaging, and dispensing systems available for his use. It also suggests criteria for selecting a vendor as well as a chemical delivery and dispensing system that will serve his specific requirements.

It also gives insights to suppliers for future user needs and should assist them in long-range planning, new product development and product improvement.

This report's numerous illustrations and diagrams make it a time-saving resource for anyone involved in the IC industry. It addresses the strategic issues impacting both the user and supplier of chemicals and equipment and is written for:

  • Executive personnel of semiconductor manufacturing facilities
  • Strategic planners of semiconductor facilities
  • Buyers of chemicals and equipment for the semiconductor industry
  • Product planners of chemicals and equipment to the semiconductor industry
  • Chemical and equipment suppliers to the semiconductor industry
  • Investment analysts

This report examines and projects the technology of equipment and materials involved in the fabrication of VLSI semiconductor devices, their likely developments, why and when their introduction or demise will take place, what problems and choices are facing users, and where the opportunities and pitfalls are. This report discusses the technology trends, products, applications, and suppliers of chemicals (liquids and gases) and equipment (lithography, plasma etching, and CMP). It also gives insights to suppliers for future user needs and should assist them in long range planning, new product development and product improvement.

Table of Contents

Chapter 1 - Introduction

Chapter 2 - Low-K Dielectric Issues and Trends

  • 2.1. Introduction
  • 2.2. Ideal Dielectric
  • 2.3. Types of Low-K Dielectrics
    • 2.3.1. FSG
    • 2.3.2. HSQ
    • 2.3.3. Nanoporous Silica
    • 2.3.4. Spin-on Polymers
    • 2.3.5. BCB
    • 2.3.6. Flowfill
    • 2.3.7. CVD
    • 2.3.8. AF4
    • 2.3.9. PTFE
  • 2.4. Summary
    • 2.4.1. Processing Issues
    • 2.4.2. Integration Issues

Chapter 3 - Lithography Issues And Trends

  • 3.1. Optical Systems
    • 3.1.1. Step-and-Repeat Aligners
    • 3.1.2. 248nm DUV Resist
    • 3.1.3. 193nm DUV Resist
    • 3.1.4. Mix-and-Match
    • 3.1.5. Immersion Lithography
    • 3.1.6. EUV
  • 3.2. X-Ray Systems
    • 3.2.1. X-Ray Sources
    • 3.2.2. X-Ray Masks
    • 3.2.3. X-Ray Steppers
    • 3.2.4. X-Ray Resists
  • 3.3. Electron Beam Systems
  • 3.4. Ion Beam Systems
    • 3.4.1. Direct Write
    • 3.4.2. Ion Channel Masking
    • 3.4.3. Ion Projection
  • 3.5. Nano-Imprint Lithography
  • 3.6. New Technologies
    • 3.6.1. Mulith Reference Distribution Aerial Image Formation
    • 3.6.2. Holograms
    • 3.6.3. X-Ray Laser
    • 3.6.4. Atom Lithography
    • 3.6.5. Microlenses
    • 3.6.7. EWL Lithography
  • 3.7. Evaluation of Lithography Cost of Ownership
    • 3.7.1. Introduction
    • 3.6.2. Cost of Ownership Model
    • 3.6.3. Results of Cost of Ownership Calculation
    • 3.6.4. Individual Cost Estimation
      • Lithography System Cost
      • Process Costs
      • Mask Costs
  • 3.7. Conclusion

Chapter 4 - CMP Issues and Trends

  • 4.1. Need for Planarity
    • 4.1.1. Lithography
    • 4.1.2. Deposition
    • 4.1.3. Etching
  • 4.2. Applications
    • 4.2.1. Dielectrics
    • 4.2.2. Metals
  • 4.3. Planarization Techniques
    • 4.3.1. Local Planarization
      • 4.3.1.1. Deposition-Etchback
      • 4.3.1.2. ECR
      • 4.3.1.3. Oxide Reflow
      • 4.3.1.4. Spin-on-Glass
      • 4.3.1.5. TEOS-Ozone
      • 4.3.1.6. Laser
    • 4.3.2. Global Planarization
      • 4.3.2.1. Polymer
      • 4.3.2.2. Polyimide
      • 4.3.2.3. Isotropic Etch
      • 4.3.2.4. Spin Etch Planarization
      • 4.3.2.5. Electropolishing
  • 4.4. Chemical Mechanical Polishing (CMP)
    • 4.4.1. Background
    • 4.4.2. Research Efforts
    • 4.4.3. Advantages and Disadvantages
    • 4.4.4. Process Parameters
      • 4.4.4.1. STI Planarization
      • 4.4.4.2. Copper CMP
      • 4.4.4.3. Low-K Integration
      • 4.4.4.4. Defect Density
      • 4.4.4.5. Metrology
    • 4.4.5. Device Processing Parameters
      • 4.4.5.1. Memory Devices
      • 4.4.5.2. Logic Devices

Chapter 5 - Factory Automation Issues and Trends

  • 5.1. Introduction
  • 5.2. Elements of Automation
    • 5.2.1. Tool Automation
    • 5.2.2. Intrabay Automation
    • 5.2.3. Interbay Automation
    • 5.2.4. Material-Control System
  • 5.3. Flexible Automation
  • 5.4. Reliability
  • 5.5. Tool Issues and Trends
    • 5.5.1. Flexible Tool Interface
    • 5.5.2. Vacuum Robotics
    • 5.5.3. AGV
    • 5.5.4. Robot Control Systems
    • 5.5.5. 300-mm Wafer Transport
    • 5.5.6. Mini-Environments and Cleanroom Issues
  • 5.6. E-Manufacturing

Chapter 6 - Thin film Deposition Issues and Trends

  • 6.1. Physical Vapor Deposition
    • 6.1.1. Sputtering Technology
    • 6.1.2. Plasma Technology
    • 6.1.3. Reactor Designs
      • 6.1.3.1. Long-Throw Deposition
      • 6.1.3.2. Collimated Sputter Deposition
      • 6.1.3.3. Showerhead Deposition
      • 6.1.3.4. Ionized PVD
    • 6.1.4. Semiconductor Processing
      • 6.1.4.1. Feature Patterning
      • 6.1.4.2. Gap Fill
  • 6.2. Chemical Vapor Deposition (CVD) Techniques
    • 6.2.1. APCVD
    • 6.2.2. LPCVD
    • 6.2.3. PECVD
    • 6.2.4. HDPCVD
    • 6.2.5. ALD

Chapter 7 - Plasma Etching Issues and Trends

  • 7.1. Introduction
  • 7.2. Processing Issues
    • 7.2.1. Chlorine Versus Fluorine Processes
    • 7.2.2. Multilevel Structures
    • 7.2.3. New Metallization Materials
    • 7.2.4. GaAs Processing
  • 7.3. Plasma Stripping
    • 7.3.1. Photoresist Stripping
    • 7.3.2. Low-K Removal

Chapter 8 - Cluster Tools Issues and Trends

  • 8.1. Definitions
  • 8.2. Device Technology and Integrated Processing
  • 8.3. Main Functional Units
    • 8.3.1. Central Handling Platform
    • 8.3.2. Cassette Stations
    • 8.3.3. Extension Modules
    • 8.3.4. Single Process Modules
    • 8.3.5. Batch Modules
    • 8.3.6. Multiple Process Modules
  • 8.4. Cluster Tool Communications
    • 8.4.1. Cluster Tool Controller
    • 8.4.2. Transport Module Controller
    • 8.4.3. Process Module Controller
    • 8.4.4. Control Software
    • 8.4.5. Human Interface Software
    • 8.4.6. Networking Software
  • 8.5. Vacuum System Design
  • 8.6. Trends
    • 8.6.1. Deposition - Plasma Etch
    • 8.6.2. Deposition - Rapid Thermal Processing
    • 8.6.3. Lithography - Resist Processing
    • 8.6.4. Diagnostics - Process
    • 8.6.5. CMP Polish - Clean

Chapter 9 - Chemicals and Materials Issues and Trends

  • 9.1. Technology Issues
    • 9.1.1. Acids and Solvents
    • 9.1.2. Resists
  • 9.2. Purity Requirements
    • 9.2.1. Purification Methods
      • Trends For Purity - Trace Elements
    • 9.2.2. Particulates
      • Effects on Yield
      • Particulate Removal Techniques
      • Particle Monitoring
  • 9.3. Chemical Management
    • 9.3.1. Introduction
    • 9.3.2. Chemical Usage Reduction
  • 9.4. Gases
    • 9.4.1. Requirements
      • 9.4.1.1. Purification Alternatives
    • 9.4.2. Particulate Considerations
      • 9.4.2.1. Particle Monitoring
      • 9.4.2.2. Filtration Methods
    • 9.4.3. Summary
  • 9.5. Sputtering and Evaporation Materials
    • 9.5.1. Technology Issues
    • 9.5.2. Purity Requirements

Chapter 10 - Contamination Issues and Trends

  • 10.1. Liquid Chemicals
    • 10.1.1. Purification Methods
    • 10.1.2. Particulates
      • Effects on Yield
      • Particulate Removal
      • Particle Monitoring
    • 10.1.3. Bulk Distribution vs Bottles
    • 10.1.4. Piping System Construction
      • Materials of Construction
      • Cost Analysis
  • 10.2. Gases
    • 10.2.1. Technology Issues
    • 10.2.2. Requirements
      • Purification Alternatives
      • Purity Trends
      • Particulate Considerations
  • 10.3. Deionized Water
    • 10.3.1. Purification Specifications
    • 10.3.2. Purification Methods
    • 10.3.3 Purity Measurement Techniques
    • 10.3.4 Filtration And Ultrafiltration
    • 10.3.5. Piping System Construction
    • 10.3.6 DI Water System Costs
  • 10.4. Processing Equipment
    • 10.4.1. Detection Methods
    • 10.4.2. Removal Techniques

Chapter 11 - Metrology

  • 11.1. Defect Review/Wafer Inspection
    • 11.1.2. Defect Review
      • 11.1.2.1. SEM Defect Review
      • 11.1.2.2. Optical Defect Review
      • 11.1.2.3. Other Defect Review
    • 11.1.3. Patterned Wafer Inspection
      • 11.1.3.1. E-Beam Patterned Wafer Inspection
      • 11.1.3.2. Optical Patterned Wafer Inspection
    • 11.1.4. Unpatterned Wafer Inspection
    • 11.1.5. Macro-Defect Inspection
  • 11.2 Thin Film Metrology
    • 11.2.1. Metal Thin-Film Metrology
    • 11.2.2. Non-Metal Thin-Film Metrology
    • 11.2.3. Substrate Metrology
  • 11.3. Lithography Metrology
    • 11.3.1. Overlay
    • 11.3.2. CD
    • 11.3.3. Mask (Reticle) Metrology/Inspection

Chapter 12 - Market Forecast

  • 12.1. Market Drivers
    • 12.1.1 Semiconductor Market
    • 12.1.2 Technical Trends
    • 12.1.3 Economic Trends
    • 12.1.4 Geographic Trends
      • 12.1.1.1. China
      • 12.1.4.2. Asia
      • 12.1.4.3. Europe
      • 12.1.4.4. Japan
      • 12.1.4.5. United States
  • 12.2. Market Forecast Assumptions
  • 12.3. Low-K Market
  • 12.4. Lithography Market
  • 12.5. CMP Market
    • 12.5.1. CMP Polisher Market
    • 12.5.2. CMP Slurry Market
  • 12.6. Factory Automation Market
  • 12.7. Thin Film Deposition Market
    • 12.7.1. Chemical Vapor Deposition Market
    • 12.7.2. Physical Vapor Deposition Market
  • 12.8. Plasma Etching Market
  • 12.9. Cluster Tool Market
    • 12.9.1. Flexible Cluster Tool Market
    • 12.9.2. Non-Flexible Cluster Tool Market
  • 12.10. Chemical and Materials Market
    • 12.10.1. Forecast by Chemical and Material
    • 12.10.2. Market Shares
  • 12.11. Cleanroom and Contamination Market
  • 12.12. Metrology Market

FIGURES

  • 2.1. Interconnect Delay for Copper/Low-K
  • 3.1. Lithography Roadmap
  • 3.2. Lens Arrangement For Submicron Features
  • 3.3. Advanced Optical Lithography Scenarios
  • 3.4. Mix-and-Match Approaches
  • 3.5. High Index Refractive Materials
  • 3.6. EUV Lithography
  • 3.7. Illustration of X-Ray Lithography
  • 3.8. Schematic Of Scalpel Electron Beam System
  • 3.9. Multi-Source E-Beam Lithography
  • 3.10. Principles of LEEPL
  • 3.11. Ion Projection Lithography System
  • 3.12. Hermoplastic Nanoimprint Lithography Process
  • 3.13. Step And Flash Nanoimprint Lithography Process
  • 3.14. Mulith Reference Distribution Aerial Image Formation
  • 3.15. Schematic of Microlens
  • 3.16. Mapper Mask-Based Lithography
  • 3.17. Mapper Maskless Lithography
  • 3.18. CoO Value in DRAM Mass Production
  • 3.19. Lithography Costs for 40,000 Wafers/Mask
  • 3.20. Lithography Costs for 1,000 Wafers/Mask
  • 4.1. Planarization Lengths of Various Methods
  • 4.2. Normalized Removal Rates
  • 4.3. Reduced Complexity With Copper
  • 4.4. Copper Loss From CMP
  • 4.5. CMP Copper Process Technologies
  • 4.6. CMP Performance Improvements
  • 4.7. Polish Endpoint Control
  • 5.1. Material-Control System
  • 5.2. Traditional and Flexible Automated Material Handling System
  • 5.3. Overhead Monorail Delivery - Cassette in Box, Cassette in SMIF Pod
  • 5.4. Stocker Design and Interfaces
  • 5.5. Layout Of a 45nm 300mm Fab
  • 5.6. Interfaces To Factory Automation Systems
  • 6.1. Schematic Of Sputtering System
  • 6.2. Magnetron Sputtering Design
  • 6.3. Showerhead Reactor Design
  • 6.4. Ionized PVD
  • 6.5. APCVD Reactor
  • 6.6. Tube CVD Reactor
  • 6.7. HDPCVD Reactor
  • 6.8. ALD Versus PVD Copper Barrier
  • 7.1. Various Enhanced Designs (a) Helicon, (b) Multiple ECR, (c) Helical Resonator
  • 7.2. Schematic of Inductively Coupled Plasma Source
  • 7.3. Schematic of the HRe Source
  • 7.4. Schematic of the Dipole Magnet Source
  • 7.5. Schematic of Chemical Downstream Etch
  • 7.6. Silicon Trench Structure
  • 7.7. Dual Damascene Dielectric Etch Approaches
  • 8.1. Basic Cluster Tool Architecture
  • 8.2. Basic Cluster Tool Architecture
  • 8.3. Communications Architecture In A Cluster Tool
  • 9.1. Relationship Between Device Yield and Particles
  • 9.2. Relationship Between Die Yield and Chip Size
  • 9.3. Chemical Management Services Tasks
  • 9.4. ITRS Roadmap
  • 9.5. Gate-Last Approach
  • 9.6. Gate-First Approach
  • 10.1. Relationship Between Device Yield and Particles
  • 10.2. Relationship Between Die Yield and Cost Size
  • 10.3. Sources of Particles
  • 11.1. Thin Film Metrology Challenges
  • 11.2. Spectroscopic Ellipsometry Diagram
  • 11.3. ITRS Overlay Technology Roadmap
  • 11.4. NIST Line Edge Roughness Model
  • 11.5. ITRS Metrology Roadmap
  • 11.6. Schematic Of OCD Optics
  • 11.7. Microlithography Process And Measurements
  • 12.1. Low-K Deposition Market Shares
  • 12.2. Worldwide Lithography Market Shares
  • 12.3. Semiconductor Equipment Utilization
  • 12.4. Market Shares of Automated Wafer Transfer Suppliers
  • 12.5. Worldwide MCVD Market Shares
  • 12.6. Worldwide DCVD Market Shares
  • 12.7. Worldwide PVD Market Shares
  • 12.8. Worldwide Market Shares for Dry Etch Equipment
  • 12.9. Distribution of Etch Sales by Type
  • 12.10. Market Forecast of Flexible Cluster Tools
  • 12.11. Market Shares of Flexible Cluster Tools
  • 12.12. Market Forecast of Non-Flexible Cluster Tools
  • 12.13. Market Shares of Non-Flexible Cluster Tools
  • 12.14. Worldwide Market Shares of Sputtering Target Suppliers
  • 12.15. Worldwide Market Shares of Liquid Chemical Suppliers
  • 12.16. Worldwide Market Shares of Photoresist Suppliers
  • 12.17. Worldwide Market Shares of Silicon Wafer Suppliers
  • 12.18. Worldwide Market Shares of Gas Suppliers
  • 12.19. Total Metrology Market Forecast
  • 12.20. Total Metrology Market Shares

TABLES

  • 2.1. Low-K Material Requirements
  • 2.2. Low-K Materials
  • 3.1. Lithography Requirements for IC Production
  • 3.2. Characteristics of X-Ray Systems
  • 3.3. Basic Conditions of CoO Model
  • 3.4. Calculation List of Lithography System Cost
  • 3.5. Throughput Estimation of X-Ray Lithography
  • 3.6. Cost of Reticle/X-Ray Mask
  • 3.7. Phase Shift Mask and X-Ray Mask Manufacturing
  • 4.1. Levels of Integration of Dynamic Rams
  • 4.2. Interconnect Levels of Logic Device
  • 4.3. Typical Process Specifications
  • 4.4. Organic Polymers for IMD Applications
  • 4.5. CMP Process Variables
  • 4.7. Optimized CMP and Post-CMP Clean Parameters
  • 4.8. Interconnect Materials by Segment
  • 5.1. Evolution Of Factory Metrics
  • 7.1. Silicon Wafer Usage
  • 7.2. Plasma Source Comparison
  • 7.3. Typical Process Specifications
  • 7.4. Dry Resist Stripping Systems
  • 8.1. Model for DRAM Production Line
  • 9.1. Common Wafer Processing Chemicals
  • 9.2. Photoresist Stripping Solutions
  • 9.3. Potential Hazards of Processing Gases
  • 10.1. Advantages and Disadvantages of Various Cleaning Methods
  • 10.2. Chemical and Material Compatibility
  • 10.3. Piping System Economic Analysis for Positive Developer
  • 10.4. Gas Control System Issues
  • 10.5. Range of Purity of CVD Gases
  • 10.6. Potential Hazards of Processing Gases
  • 10.7. Particle Sources
  • 10.8. Location of In-Situ Monitors by Equipment Type
  • 11.1. Comparison Of White-Light With Multiple-Angle Laser Ellipsometry
  • 12.1. Worldwide Capital Spending 2005-2011
  • 12.2. Worldwide GDP 1997-2011
  • 12.3. Worldwide Market Forecast Low-K Market
  • 12.4. Worldwide Stepper Market
  • 12.5. Worldwide CMP Polisher Market
  • 12.6. Worldwide CMP Market Shares
  • 12.7. Worldwide CMP Slurry Market
  • 12.8. Worldwide Forecast of Automated Transfer Tools
  • 12.9. Worldwide CVD Market Forecast
  • 12.10. Worldwide PVD Market Forecast
  • 12.11. Worldwide Market Forecast of Plasma Etching Systems
  • 12.12. Worldwide Forecast of Chemicals and Materials
  • 12.13. Worldwide Wafer Fab Construction Spending Forecast
  • 12.14. Total Metrology Market Forecast
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