The Global Market for Advanced Semiconductor Packaging 2027-2037

Table of Contents

1 EXECUTIVE SUMMARY

• 1.1 Semiconductor Packaging Technology Overview
  • 1.1.1 Key challenges
  • 1.1.2 Evolution of semiconductor packaging
    • 1.1.2.1 From 1D to 3D
  • 1.1.3 Conventional packaging approaches
  • 1.1.4 Advanced packaging approaches
• 1.2 Semiconductor Supply Chain
• 1.3 Advanced Packaging Supply Chain
• 1.4 Key Technology Trends in Advanced Packaging
• 1.5 Market Growth Drivers
• 1.6 Competitive Landscape
• 1.7 Market Challenges
• 1.8 Future outlook
  • 1.8.1 Heterogeneous Integration
  • 1.8.2 Chiplets and Die Disaggregation
  • 1.8.3 Advanced Interconnects
  • 1.8.4 Scaling and Miniaturization
  • 1.8.5 Thermal Management
  • 1.8.6 Materials Innovation
  • 1.8.7 Supply Chain Developments
  • 1.8.8 Role of Simulation and Data Analytics

2 SEMICONDUCTOR PACKAGING TECHNOLOGIES

• 2.1 Transistor Device Scaling
  • 2.1.1 Overview
  • 2.1.2 Heterogeneous Architecture Transition
  • 2.1.3 Co-Design Focus Areas
• 2.2 Wafer Level Packaging
• 2.3 Fan-Out Wafer Level Packaging
• 2.4 Chiplets
  • 2.4.1 AMD EPYC and Ryzen processor families
  • 2.4.2 Disaggregation Needs
• 2.5 Interconnection in Semiconductor Packaging
  • 2.5.1 Overview
  • 2.5.2 Wire Bonding
  • 2.5.3 Flip-chip bonding
  • 2.5.4 Interposer
    • 2.5.4.1 Interposer technology comparison
    • 2.5.4.2 Glass interposer
      • 2.5.4.2.1 Technical challenge of glass interposer
      • 2.5.4.2.2 Different Interposer material comparison
  • 2.5.5 Through-silicon via (TSV) bonding
  • 2.5.6 Hybrid bonding with chiplets
  • 2.5.7 Re-architecting die-to-die I/O
• 2.6 2.5D and 3D Packaging
  • 2.6.1 2.5D packaging
    • 2.6.1.1 Overview
      • 2.6.1.1.1 Silicon Interposer 2.5D
        • 2.6.1.1.1.1 Through Si Via (TSV)
        • 2.6.1.1.1.2 (SiO2) based redistribution layers (RDLs)
      • 2.6.1.1.2 2.5D Organic-based packaging
        • 2.6.1.1.2.1 Chip-first and chip-last fan-out packaging
        • 2.6.1.1.2.2 Organic substrates
        • 2.6.1.1.2.3 Organic RDL
      • 2.6.1.1.3 2.5D glass-based packaging
        • 2.6.1.1.3.1 Benefits
        • 2.6.1.1.3.2 Glass Si interposers in advanced packaging
        • 2.6.1.1.3.3 Glass material properties
        • 2.6.1.1.3.4 2/2 μm line/space metal pitch on glass substrates
        • 2.6.1.1.3.5 3D Glass Panel Embedding (GPE) packaging
        • 2.6.1.1.3.6 Thermal management
        • 2.6.1.1.3.7 Polymer dielectric films
        • 2.6.1.1.3.8 Challenges
        • 2.6.1.1.3.9 Comparison with other substrates
        • 2.6.1.1.3.10 TGV formation and metallisation
      • 2.6.1.1.4 2.5D vs. 3D Packaging
    • 2.6.1.2 Benefits
    • 2.6.1.3 Challenges
    • 2.6.1.4 Trends
    • 2.6.1.5 Market players
  • 2.6.2 3D packaging
    • 2.6.2.1 Conventional 3D packaging
    • 2.6.2.2 Advanced 3D Packaging with through-silicon vias (TSVs)
    • 2.6.2.3 W2W vs D2W vs Collective D2W
    • 2.6.2.4 Direct Molecular Bonding
    • 2.6.2.5 3D Interconnect Trends
    • 2.6.2.6 Hybrid Bonding
      • 2.6.2.6.1 Devices using hybrid bonding
      • 2.6.2.6.2 Fusion Bond
      • 2.6.2.6.3 Low- and room-temperature Cu-Cu bonding
      • 2.6.2.6.4 Devices using hybrid bonding
    • 2.6.2.7 3D stacking supply chain
    • 2.6.2.8 3D Microbump technology
      • 2.6.2.8.1 Technologies
      • 2.6.2.8.2 Challenges
      • 2.6.2.8.3 Bumpless copper-to-copper (Cu-Cu) hybrid bonding
    • 2.6.2.9 Trends
      • 2.6.2.9.1 Memory drives the next wave
      • 2.6.2.9.2 Low- and room-temperature Cu-Cu bonding

3 WAFER-LEVEL PACKAGING

• 3.1 Introduction
  • 3.1.1 WLP to PLP
• 3.2 Benefits
• 3.3 Types of Wafer Level Packaging
  • 3.3.1 Wafer Level Chip Scale Packaging
    • 3.3.1.1 Overview
    • 3.3.1.2 Advantages
    • 3.3.1.3 Applications
  • 3.3.2 Wafer Level Fan-Out Packaging
    • 3.3.2.1 Overview
    • 3.3.2.2 Advantages
    • 3.3.2.3 Applications
  • 3.3.3 Wafer Level Fan-In Packaging
    • 3.3.3.1 Overview
    • 3.3.3.2 Advantages
    • 3.3.3.3 Applications
  • 3.3.4 Other Types of WLP
    • 3.3.4.1 Cu-Pillar Flip Chip
    • 3.3.4.2 Advantages
      • 3.3.4.2.1 Applications
    • 3.3.4.3 Embedded Wafer Level BGA (eWLB)
    • 3.3.4.4 Advantages
      • 3.3.4.4.1 Applications
    • 3.3.4.5 Chip-last FO-WLP
      • 3.3.4.5.1 Advantages
      • 3.3.4.5.2 Applications
    • 3.3.4.6 Wafer-on-Wafer (WoW)
      • 3.3.4.6.1 Applications
• 3.4 WLP Manufacturing Processes
  • 3.4.1 Wafer Preparation
  • 3.4.2 RDL Buildup
  • 3.4.3 Bumping
  • 3.4.4 Encapsulation
  • 3.4.5 Integration
  • 3.4.6 Test and Singulation
• 3.5 Wafer Level Packaging Trends
• 3.6 Applications of Wafer Level Packaging
  • 3.6.1 Mobile and Consumer Electronics
  • 3.6.2 Automotive Electronics
  • 3.6.3 IoT and Industrial
  • 3.6.4 High Performance Computing
  • 3.6.5 Aerospace and Defense
• 3.7 Wafer Level Packaging Outlook

4 SYSTEM-IN-PACKAGE AND HETEROGENEOUS INTEGRATION

• 4.1 Introduction
• 4.2 Approaches for heterogenous integration
  • 4.2.1 Technology Building Blocks
• 4.3 SiP Manufacturing Approaches
  • 4.3.1 2.5D Integrated Interposers
  • 4.3.2 Multi-Chip Modules
  • 4.3.3 3D Stacked packages
  • 4.3.4 Fan-Out Wafer Level Packaging
  • 4.3.5 Flip Chip Package-on-Package
• 4.4 SiP Component Integration
• 4.5 Heterogeneous Integration Drivers
• 4.6 Trends Driving SiP Adoption
• 4.7 SiP Applications
• 4.8 SiP Industry Landscape
• 4.9 Future Outlook on Heterogeneous Integration
• 4.10 CPO (Co-Packaged Optics)
  • 4.10.1 Co-packaging approaches
  • 4.10.2 Heterogeneous integration of EIC and PIC
  • 4.10.3 Interconnect Technology (in CPO)
  • 4.10.4 Type of couplers
  • 4.10.5 Advantages and limitations
  • 4.10.6 CPO technologies, by company
• 4.11 IC Substrates

5 MONOLITHIC 3D IC

• 5.1 Overview
  • 5.1.1 Transitioning from 2D Systems
  • 5.1.2 Motivation for developing monolithic 3D manufacturing
  • 5.1.3 Improved M3D Interconnect Density
  • 5.1.4 Heterogenous 3D vs Monolithic 3D
  • 5.1.5 2D Materials
• 5.2 Benefits
• 5.3 Challenges
• 5.4 Future outlook

6 MARKETS AND APPLICATIONS

• 6.1 Market value chain
  • 6.1.1 SiP OEM/Designers
  • 6.1.2 Chiplet OEM/Designer and Chiplet Foundry
  • 6.1.3 Chiplet Integrator
    • 6.1.3.1 Integrated Device Manufacturers (IDMs)
    • 6.1.3.2 Outsourced Semiconductor Assembly and Test (OSAT) Providers
  • 6.1.4 Material Suppliers
  • 6.1.5 Equipment Suppliers
  • 6.1.6 Substrate and PCB suppliers
  • 6.1.7 EDA Tools Suppliers
  • 6.1.8 Interposer Foundry
• 6.2 Packaging trends by market
  • 6.2.1 Mobile Devices
  • 6.2.2 High-Performance Computing (HPC)
  • 6.2.3 Automotive
  • 6.2.4 Internet of Things (IoT)
  • 6.2.5 Consumer Electronics
  • 6.2.6 Aerospace and Defense
  • 6.2.7 Medical Devices
• 6.3 Design requirements
• 6.4 Artificial Intelligence (AI)
  • 6.4.1 Challenges in AI
  • 6.4.2 Advanced Packaging Solutions
    • 6.4.2.1 2.5D and 3D Integration
    • 6.4.2.2 Chiplet-based Packaging
    • 6.4.2.3 Wafer-Level Packaging (WLP)
  • 6.4.3 Addressing AI Challenges through Advanced Packaging
    • 6.4.3.1 Processing Power
    • 6.4.3.2 Memory Bandwidth
    • 6.4.3.3 Energy Efficiency
    • 6.4.3.4 Scalability
  • 6.4.4 Applications
    • 6.4.4.1 Data Center and Cloud Computing
    • 6.4.4.2 Edge Devices and IoT
    • 6.4.4.3 Healthcare and Medical Devices
    • 6.4.4.4 Autonomous Vehicles
• 6.5 Mobile Devices
  • 6.5.1 Challenges
  • 6.5.2 Advanced Packaging Solutions
    • 6.5.2.1 System-in-Package (SiP)
    • 6.5.2.2 Fan-Out Wafer-Level Packaging (FOWLP)
    • 6.5.2.3 3D IC Packaging
    • 6.5.2.4 Wafer-Level Chip-Scale Packaging (WLCSP)
  • 6.5.3 Addressing Challenges through Advanced Packaging
    • 6.5.3.1 Power Consumption and Thermal Management
    • 6.5.3.2 Size Constraints
    • 6.5.3.3 Cost
  • 6.5.4 Applications
    • 6.5.4.1 Smartphones
    • 6.5.4.2 Tablets
    • 6.5.4.3 Wearables
    • 6.5.4.4 AR/VR Devices
  • 6.5.5 Future trends
• 6.6 High Performance Computing (HPC)
  • 6.6.1 Challenges
  • 6.6.2 Advanced Packaging Solutions for HPC
    • 6.6.2.1 2.5D and 3D Integration
    • 6.6.2.2 Hybrid bonding
    • 6.6.2.3 Multi-Chip Modules (MCMs)
    • 6.6.2.4 Chiplet-based Architectures
    • 6.6.2.5 Advanced Interconnect Technologies
  • 6.6.3 Addressing HPC Challenges through Advanced Packaging
    • 6.6.3.1 Performance Scaling
    • 6.6.3.2 Power Consumption
    • 6.6.3.3 Interconnect Bandwidth
    • 6.6.3.4 Reliability
  • 6.6.4 Applications
    • 6.6.4.1 Supercomputers
    • 6.6.4.2 Data Center and Cloud Computing
    • 6.6.4.3 Artificial Intelligence and Machine Learning
    • 6.6.4.4 Scientific Computing and Simulation
    • 6.6.4.5 Co-Packaged Optics
      • 6.6.4.5.1 Network Switch
      • 6.6.4.5.2 Optical communication in data centers
      • 6.6.4.5.3 Thermal Management
      • 6.6.4.5.4 Challenges in CPO
      • 6.6.4.5.5 Package Structure
      • 6.6.4.5.6 Fan-Out Embedded Bridge (FOEB) structure
      • 6.6.4.5.7 Advancing Switching and AI Networks
      • 6.6.4.5.8 Making on-chip photonics manufacturable
  • 6.6.5 Thermal Interface Materials
  • 6.6.6 Future Trends
• 6.7 Automotive Electronics
  • 6.7.1 Challenges
  • 6.7.2 Advanced Packaging Solutions for Automotive Electronics
    • 6.7.2.1 System-in-Package (SiP)
    • 6.7.2.2 Flip-Chip and Wafer-Level Packaging (WLP)
    • 6.7.2.3 3D Integration and Through-Silicon Vias (TSVs)
  • 6.7.3 Addressing Automotive Electronics Challenges through Advanced Packaging
    • 6.7.3.1 ADAS/Autonomous driving systems
    • 6.7.3.2 Harsh Environment Reliability
    • 6.7.3.3 Safety and Reliability
    • 6.7.3.4 Miniaturization and Integration
    • 6.7.3.5 High-Speed Communication
    • 6.7.3.6 Thermal Management
  • 6.7.4 Applications
    • 6.7.4.1 Advanced Driver Assistance Systems (ADAS) and Autonomous Driving
      • 6.7.4.1.1 Radar packaging
    • 6.7.4.2 Electric Vehicle (EV) Power Electronics
    • 6.7.4.3 Infotainment and Telematics
    • 6.7.4.4 Sensors and Actuators
  • 6.7.5 Future Trends
• 6.8 Internet of Things (IoT) Devices
  • 6.8.1 Challenges
  • 6.8.2 Advanced Packaging Solutions for IoT Devices
    • 6.8.2.1 Wafer-Level Packaging (WLP)
    • 6.8.2.2 System-in-Package (SiP)
    • 6.8.2.3 Fan-Out Wafer-Level Packaging (FOWLP)
    • 6.8.2.4 3D Packaging and Through-Silicon Vias (TSVs)
  • 6.8.3 Addressing IoT Device Challenges through Advanced Packaging
    • 6.8.3.1 Size Constraints
    • 6.8.3.2 Power Consumption
    • 6.8.3.3 Cost Pressures
    • 6.8.3.4 Integration and Functionality
    • 6.8.3.5 Reliability and Robustness
  • 6.8.4 Applications
    • 6.8.4.1 Wearable Devices
    • 6.8.4.2 Smart Home Devices
    • 6.8.4.3 Industrial IoT Devices
    • 6.8.4.4 Medical IoT Devices
  • 6.8.5 Future Trends
• 6.9 5G & 6G Communications Infrastructure
  • 6.9.1 Challenges
  • 6.9.2 Trends in 5G and 6G packaging
  • 6.9.3 Advanced Packaging Solutions for 5G and 6G Communications Infrastructure
    • 6.9.3.1 Antenna-in-Package (AiP)
    • 6.9.3.2 System-in-Package (SiP)
    • 6.9.3.3 3D Packaging and Through-Silicon Vias (TSVs)
    • 6.9.3.4 Fan-Out Wafer-Level Packaging (FOWLP)
  • 6.9.4 Addressing 5G and 6G Infrastructure Challenges through Advanced Packaging
    • 6.9.4.1 High-Frequency Operation
    • 6.9.4.2 Massive MIMO and Beamforming
    • 6.9.4.3 Energy Efficiency
    • 6.9.4.4 Cost and Scalability
    • 6.9.4.5 Thermal Management
  • 6.9.5 Applications
    • 6.9.5.1 Base Stations and Small Cells
    • 6.9.5.2 Backhaul and Fronthaul Networks
    • 6.9.5.3 Edge Computing and Network Slicing
    • 6.9.5.4 Satellite and Non-Terrestrial Networks
  • 6.9.6 Future Trends
• 6.10 Aerospace and Defense Electronics
  • 6.10.1 Challenges
  • 6.10.2 Advanced Packaging Solutions for Aerospace and Defense Electronics
    • 6.10.2.1 3D Packaging and Through-Silicon Vias (TSVs)
    • 6.10.2.2 Chip-Scale Packaging (CSP) and Wafer-Level Packaging (WLP)
    • 6.10.2.3 Flip-Chip and Ball Grid Array (BGA) Packaging
    • 6.10.2.4 Hermetic Packaging and Sealing
  • 6.10.3 Addressing Aerospace and Defense Electronics Challenges through Advanced Packaging
    • 6.10.3.1 Size, Weight, and Power (SWaP) Optimization
    • 6.10.3.2 Harsh Environment Reliability
    • 6.10.3.3 High Performance and Speed
    • 6.10.3.4 Long-Term Reliability and Maintainability
    • 6.10.3.5 Security and Anti-Tamper Features
  • 6.10.4 Applications
    • 6.10.4.1 Avionics and Flight Control Systems
    • 6.10.4.2 Radar and Electronic Warfare Systems
    • 6.10.4.3 Satellite Communications and Payload Electronics
    • 6.10.4.4 Missile Guidance and Control Electronics
  • 6.10.5 Future Trends
• 6.11 Medical Electronics
  • 6.11.1 Challenges
  • 6.11.2 Advanced Packaging Solutions for Medical Electronics
    • 6.11.2.1 3D Packaging and Through-Silicon Vias (TSVs)
    • 6.11.2.2 Wafer-Level Packaging (WLP) and Chip-Scale Packaging (CSP)
    • 6.11.2.3 Flexible and Stretchable Packaging
    • 6.11.2.4 Microfluidic Packaging
  • 6.11.3 Addressing Medical Electronics Challenges through Advanced Packaging
    • 6.11.3.1 Miniaturization
    • 6.11.3.2 Biocompatibility
    • 6.11.3.3 Reliability
    • 6.11.3.4 Power Efficiency
    • 6.11.3.5 High Performance
  • 6.11.4 Applications
    • 6.11.4.1 Implantable Devices
    • 6.11.4.2 Wearable Health Monitors
    • 6.11.4.3 Diagnostic Imaging Equipment
    • 6.11.4.4 Surgical Robotics and Instruments
  • 6.11.5 Future Trends
• 6.12 Consumer Electronics
  • 6.12.1 Challenges
  • 6.12.2 Advanced Packaging Solutions for Consumer Electronics
    • 6.12.2.1 System-in-Package (SiP)
    • 6.12.2.2 Fan-Out Wafer-Level Packaging (FOWLP)
    • 6.12.2.3 3D Packaging and Through-Silicon Vias (TSVs)
    • 6.12.2.4 Embedded Die Packaging
  • 6.12.3 Addressing Consumer Electronics Challenges through Advanced Packaging
    • 6.12.3.1 Miniaturization
    • 6.12.3.2 Power Efficiency
    • 6.12.3.3 High Performance
    • 6.12.3.4 Cost Reduction
    • 6.12.3.5 Time-to-Market
  • 6.12.4 Applications
    • 6.12.4.1 Smartphones and Tablets
    • 6.12.4.2 Wearables and IoT Devices
    • 6.12.4.3 Gaming Consoles and VR/AR Devices
    • 6.12.4.4 Smart Home Devices
  • 6.12.5 Future Trends
• 6.13 Additive manufacturing for advanced packaging
• 6.14 Silicon photonics

7 GLOBAL MARKET FORECASTS

• 7.1 By type
• 7.2 By Units & Wafers
• 7.3 By end-use market
• 7.4 By region
• 7.5 3D SoC
• 7.6 3D Stacked memory
• 7.7 UHD FO / RDL Interposer
• 7.8 2.5D Interposers
• 7.9 Embedded Si bridge

8 MARKET TRENDS

• 8.1 Data center
• 8.2 AI and Graphics
• 8.3 CPU
• 8.4 Autonomous vehicles
• 8.5 Roadmap
  • 8.5.1 Interconnect technology trend
  • 8.5.2 By interconnect density and technology node
  • 8.5.3 By reticle size
  • 8.5.4 By front-end vs back-end
  • 8.5.5 By 2.5D and 3D Technology Trends
  • 8.5.6 By I/O density, I/O pitch and package size
• 8.6 Commercialized Products
  • 8.6.1 3D Memory
  • 8.6.2 GPU
    • 8.6.2.1 Nvidia
    • 8.6.2.2 AMD
    • 8.6.2.3 Intel
  • 8.6.3 AI ASICs
    • 8.6.3.1 Intel
    • 8.6.3.2 Google
    • 8.6.3.3 Amazon
    • 8.6.3.4 Microsoft
    • 8.6.3.5 Huawei
    • 8.6.3.6 Meta
  • 8.6.4 CPU
    • 8.6.4.1 AMD
    • 8.6.4.2 Amazon
    • 8.6.4.3 Intel
    • 8.6.4.4 Nvidia
  • 8.6.5 Networking and CPO switches
    • 8.6.5.1 Nvidia Quantum-X and Spectrum-X Photonics
    • 8.6.5.2 Broadcom Tomahawk CPO (Bailly / Davisson)

9 MARKET PLAYERS

• 9.1 Integrated Device Manufacturers
• 9.2 Outsourced Semiconductor Assembly and Test (OSAT) Companies
• 9.3 Foundries
• 9.4 Electronics OEMs
• 9.5 Packaging Equipment and Materials Companies

10 MARKET CHALLENGES

11 COMPANY PROFILES

• 11.1 AaltoSemi
• 11.2 Absolic, Inc.
• 11.3 ACCRETECH (Europe) GmbH
• 11.4 Adeia, Inc.
• 11.5 Advanced Micro Devices, Inc. (AMD)
• 11.6 Ajinomoto
• 11.7 Analog Devices, Inc. (ADI)
• 11.8 Amkor Technology
• 11.9 Anmuquan Intelligent Technology (AMQ Intelligent)
• 11.10 Apple
• 11.11 Applied Materials
• 11.12 Ardentec Corporation
• 11.13 Arieca
• 11.14 ARM
• 11.15 ASE
• 11.16 ASMPT Ltd
• 11.17 Ayar Labs
• 11.18 Besi
• 11.19 Biren Technology
• 11.20 Blue Ocean Smart System
• 11.21 Brewer Science
• 11.22 Broadcom
• 11.23 BroadPak
• 11.24 Cadence Design Systems
• 11.25 Cambricon Technologies Co.
• 11.26 Capcon Semiconductor
• 11.27 CAS Microelectronics Integration
• 11.28 CD Micro-Technology
• 11.29 CEA-Leti
• 11.30 Cerebras
• 11.31 China Wafer Level CSP Co
• 11.32 Chipbond Technology Corporation
• 11.33 Chipletz
• 11.34 ChipMOS Technologies, Inc.
• 11.35 Coherent
• 11.36 Corning
• 11.37 Dai Nippon Printing (DNP)
• 11.38 Dewo Advanced Automation (DAA)
• 11.39 Disco
• 11.40 Dupont
• 11.41 Ebara
• 11.42 Eliyan
• 11.43 EMC Semi-Conductor Technology
• 11.44 EPS Technology
• 11.45 Entegris
• 11.46 EV Group
• 11.47 GlobalFoundries
• 11.48 Global Unichip
• 11.49 Gloway
• 11.50 Goldenscope Tech
• 11.51 Gona Semiconductor Technology
• 11.52 Graphcore
• 11.53 Greatek Electronics Inc
• 11.54 Hangke Chuangxing (Aero Inno-Star)
• 11.55 Hanmi Semiconductor
• 11.56 HD Microsystems
• 11.57 HiSilicon
• 11.58 HLMC (Shanghai Huali Microelectronics Corporation)
• 11.59 Huatian Huichuang Technology (Xi'an) Co., Ltd.
• 11.60 Huawei
• 11.61 Ibiden
• 11.62 IBM
• 11.63 ICLeague Technology Co Ltd
• 11.64 IMEC
• 11.65 Indium Corporation
• 11.66 Infineon Technologies AG
• 11.67 Integra
• 11.68 Inari Amertron Berhad
• 11.69 Intel Corporation
• 11.70 JCET Group
• 11.71 Jiangsu IC Assembly & Test (ICAT)
• 11.72 Jingdu Semiconductor
• 11.73 Keyang Semiconductor (KYS)
• 11.74 King Yuan Electronics Co., Ltd.
• 11.75 Kioxia
• 11.76 KyLitho
• 11.77 Kyocera
• 11.78 Lam Research
• 11.79 Lapis Technology
• 11.80 LB Semicon Co Ltd
• 11.81 Leading Interconnect Semiconductor Technology
• 11.82 LG Innotek
• 11.83 Lidrotec GmbH
• 11.84 Lux Semiconductors
• 11.85 Malaysian Pacific Industries Berhad
• 11.86 Micron Technology, Inc.
• 11.87 Mediatek
• 11.88 Micross Components
• 11.89 Mitsubishi
• 11.90 National Center For Advanced Packaging China (NCAP China)
• 11.91 NEC
• 11.92 Nvidia Corporation
• 11.93 Nepes Corporation
• 11.94 Nippon Electric Glass (NEG)
• 11.95 Onsemi
• 11.96 Orient Semiconductor Electronics Ltd.
• 11.97 Panasonic
• 11.98 Plan Optik AG
• 11.99 Powertech Technology Inc.
• 11.100 Pragmatic Semiconductor
• 11.101 Qorvo
• 11.102 Renesas
• 11.103 Rigger Micro Technologies (RMT)
• 11.104 Rohm
• 11.105 Rong Semiconductor
• 11.106 Samsung Electronics
• 11.107 Samtec, Inc.
• 11.108 Schott AG
• 11.109 Sharp
• 11.110 Shinko Electric Industries
• 11.111 Showa Denko (Resonac)
• 11.112 Sigurd Microelectronics Corporation
• 11.113 Silicon Box
• 11.114 Siliconware Precision Industries (SPIL)
• 11.115 SJ Semiconductor
• 11.116 SK Hynix
• 11.117 Skywater
• 11.118 Sony Corporation
• 11.119 Starmask
• 11.120 STMicroelectronics
• 11.121 Suss Microtec
• 11.122 Synopsys
• 11.123 SZLQ Intelligence (Suzhou Lieqi Intelligent Equipment)
• 11.124 Taiwan Semiconductor Manufacturing Company (TSMC)
• 11.125 Techsense International
• 11.126 Tezzaron Semiconductor
• 11.127 Tokyo Electron (TEL)
• 11.128 Tongfu Microelectronics Co., Ltd.
• 11.129 Toppan
• 11.130 Toray
• 11.131 Texas Instruments
• 11.132 Tokyo Electron
• 11.133 Tokyo Seimitsu Co., Ltd.
• 11.134 Tong Hsing Electronic Industries, Ltd.
• 11.135 Toshiba
• 11.136 Tower Semiconductor
• 11.137 Unimicron
• 11.138 Unisem
• 11.139 UTAC Group
• 11.140 Walton Advanced Engineering Inc.
• 11.141 Winstek Semiconductor Technology Co., Ltd.
• 11.142 Xinhe Semiconductor
• 11.143 Yibu Semiconductor
• 11.144 Yuehai Integrated

12 RESEARCH METHODOLOGY

13 REFERENCES

List of Tables

• Table 1. Evolution of semiconductor packaging.
• Table 2. Summary of key advanced semiconductor packaging approaches.
• Table 3. Key Technology Trends in Advanced Semiconductor Packaging.
• Table 4. Market Growth Drivers for advanced semiconductor packaging.
• Table 5. Challenges Facing Advanced Packaging Adoption.
• Table 6. Challenges in transistor scaling.
• Table 7. Leading-edge logic node roadmap, 2026–2030.
• Table 8. Use cases and benefits of using chiplets in semiconductor design.
• Table 9. Specifications of interconnection methods.
• Table 10. Interconnection technique in semiconductor packaging
• Table 11. Passive vs active interposer.
• Table 12. Interposer technology comparison
• Table 13. Technical challenges of glass interposer
• Table 14. Different Interposer material comparison
• Table 15. Comparative benchmark overview table of key semiconductor interconnection technologies
• Table 16. Die-to-die I/O approaches compared
• Table 17. Fan-out packaging process overview.
• Table 18. Comparison between mainstream silicon dioxide (SiO2) and leading organic dielectrics for electronic interconnect substrates.
• Table 19. Benefits of glass in 2.5D glass-based packaging.
• Table 20. Through-glass-via (TGV) formation methods compared.
• Table 21. Comparison between key properties of glass and polymer molding compounds commonly used in semiconductor packaging applications.
• Table 22. Challenges of glass semiconductor packaging.
• Table 23. Comparison between silicon, organic laminates and glass as packaging substrates.
• Table 24. Through-glass-via (TGV) formation methods compared (insert after Table 16)
• Table 25. 2.5D vs. 3D packaging.
• Table 26. 2.5D packaging challenges.
• Table 27. Market players in 2.5D packaging.
• Table 28. Glass substrate/packaging supplier landscape (2026).
• Table 29. Advantages and disadvantages of 3D packaging.
• Table 30. W2W vs D2W vs Collective D2W – Process and Comparison.
• Table 31. 3D Stacking Trends - Direct Molecular Bonding Technologies.
• Table 32. 3D interconnect trends
• Table 33. Hybrid bonding Advantages and Challenges.
• Table 34. Hybrid Bond Timeline for Chip Makers and Equipment Makers.
• Table 35. Comparison between 2.5D, 3D micro bump, and 3D hybrid bonding.
• Table 36. Challenges in scaling bumps.
• Table 37. Key methods for enabling copper-to-copper (Cu-Cu) hybrid bonding in advanced semiconductor packaging:
• Table 38. Micro bumps vs Cu-Cu bumpless hybrid bonding.
• Table 39. Panel-level packaging format scaling.
• Table 40. Benefits of Wafer-Level Packaging.
• Table 41. Types of wafer level packaging.
• Table 42. Key trends shaping wafer level packaging.
• Table 43. Packaging approaches utilized for assembling System-in-Package modules.
• Table 44. Considerations for integrating key component categories into system-in-package (SiP) modules/
• Table 45. Key factors driving adoption of heterogeneous integration through SiPs and multi-die packages.
• Table 46. Key trends influencing adoption of System-in-Package modules.
• Table 47. System-in-package (SiP) module applications.
• Table 48. Co-packaging approaches
• Table 49. Type of couplers
• Table 50. CPO advantages and limitations
• Table 51. Technologies offered by companies
• Table 52. Comparison between heterogeneous 3D integration and monolithic 3D integration.
• Table 53. Key 2D materials in monolithic 3D integrated circuits.
• Table 54. Benefits of monolithic 3D ICs.
• Table 55. Challenges of monolithic 3D ICs.
• Table 56. Advanced semiconductor packaging trends by market.
• Table 57. Design requirements in advanced packaging, by market.
• Table 58. TIM candidate benchmark
• Table 59. Wide-bandgap power semiconductors compared.
• Table 60. Global market for Advanced semiconductor packaging, 2027-2037, by packaging type, (billions USD).
• Table 61. Global market for Advanced semiconductor packaging, 2020-2035, by Units & Wafers, (billions USD).
• Table 62. Global market for Advanced semiconductor packaging, 2027-2035, by end use market (billions USD).
• Table 63. Global market for advanced semiconductor packaging, 2027–2037, by region (billions USD)
• Table 64. 3D SoC market, 2027–2037 (billions USD)
• Table 65. 3D stacked memory (HBM) packaging market, 2027–2037 (billions USD)
• Table 66. UHD FO / RDL interposer market, 2027–2037 (billions USD)
• Table 67. 2.5D interposer market, 2027–2037 (billions USD)
• Table 68. Large-format 2.5D / CoWoS roadmap.
• Table 69. Embedded Si bridge market, 2027–2037 (billions USD)
• Table 70. Interconnect technology trend
• Table 71. Roadmap By interconnect density and technology node
• Table 72. Roadmap By reticle size
• Table 73. Roadmap front-end vs back-end
• Table 74. Roadmap By 2.5D and 3D Technology Trends
• Table 75. Roadmap By I/O density, I/O pitch and package size
• Table 76. Main Global Wafer Foundry Companies 2023.
• Table 77. Market challenges for advanced semiconductor packaging.
• Table 78. AMD AI chip range.
• Table 79. Intel's products that adopt 3D FOVEROS.

List of Figures

• Figure 1. Timeline of different packaging technologies.
• Figure 2. Evolution roadmap for semiconductor packaging.
• Figure 3. Semiconductor Supply Chain.
• Figure 4. Advanced packaging supply chain.
• Figure 5. Scaling technology roadmap.
• Figure 6. Wafer-level chip scale packaging (WLCSP)
• Figure 7. Embedded wafer-level ball grid array (eWLB).
• Figure 8. Fan-out wafer-level packaging (FOWLP).
• Figure 9. Chiplet design.
• Figure 10. Chiplet SoC.
• Figure 11. 2D chip packaging.
• Figure 12. Typical structure of 2.5D IC package utilizing interposer.
• Figure 13. Fan-out chip-first process flow and Fan-out chip-last process flow.
• Figure 14. Manufacturing process for glass interposers.
• Figure 15. 3D Glass Panel Embedding (GPE) package.
• Figure 16. 3D stacking supply chain.
• Figure 17. Typical FOWLP structure.
• Figure 18. System-in-Package (SiP) for HI.
• Figure 19. 2.5D chiplet integration.
• Figure 20. Advanced packaging supply chain.
• Figure 21. Packaging of sensors used in advanced driver assistance systems (ADAS) and autonomous driving.
• Figure 22. Absolic glass substrate.
• Figure 23. AMD Radeon Instinct.
• Figure 24. AMD Ryzen 7040.
• Figure 25. Alveo V70.
• Figure 26. Versal Adaptive SOC.
• Figure 27. AMD’s MI300 chip.
• Figure 28. 12-layer HBM3.